About

Welcome to positive slack blog!

Here, I'm exploring and sharing insights on verification and digital design. At the moment, I'm focused on ASIC verification, so you can expect posts on things like SystemVerilog, UVM, Python, etc. mainly. While this is my main area, I might mix it up with some other related topics (embedded, programming) from time to time.

Who am I?

I'm an ASIC Verification Engineer by day, and technology enthusiast by night. My experience and interests cover not only verification field - I have completed projects in digital design, embedded and programming.

Why positive slack?

This term relates to digital design and Static Timing Analysis (STA). Positive (actually, non-negative) slack is a crucial requirement to make all digital circuits work. This refers to happy early days of my career, when I only started exploring RTL world and tried to meet STA requirements during synthesis.

Feedback

Feel free to leave any feedback via Github discussions.

Disclaimer

Everything I share here are my own thoughts and opinions. They're not connected to my employer in any way. I try to share accurate info, but remember, these are just my own reflections, so use them at your own risk. Enjoy reading!