Implementing JSON encoder and decoder in pure SystemVerilog

Posted on 07 Jul 2024 in Verification • Tagged with systemverilog • 2 min read

I decided that there aren't enough JSON encoders/decoders in SystemVerilog.


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Using pip to Manage HDL Components

Posted on 27 Jan 2024 in Automation • Tagged with python • 2 min read

There is no any standard package manager for HDL components. What if you take a package manager from a popular language and try to adapt it to HDL?


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Constant Reference in SystemVerilog: Is It Really Constant?

Posted on 14 Jan 2024 in Verification • Tagged with systemverilog • 4 min read

Usually, a programmer uses const ref for a method argument when they want to show an intention to have read-only variable that isn't a copy of an original one. And this works as a hint perfectly, but what 'constant' guarantees can the simulator actually provide? So, I've started digging...


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positive slack blog recharged

Posted on 26 Dec 2023 in General • Tagged with blog • 1 min read

I refactored my existing blog and move it to Pelican.


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Corsair - генератор карты контрольно-статусных регистров

Posted on 03 Sep 2021 in Automation • Tagged with python • 6 min read

Написал свой генератор карты CSR на Python и Jinja2.


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FTDI USB-FIFO или режим FT245

Posted on 16 Jul 2021 in Digital design • Tagged with fpga, ftdi, usb • 12 min read

Собрал и проверил на практике инструменты для работы с USB-FIFO чипами от FTDI на FPGA.


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Xilinx AXI Verification IP

Posted on 24 Apr 2021 in Verification • Tagged with amba, axi, fpga, vip • 6 min read

Небольшой обзор Xilinx AXI Verification IP - набора инструментов для верификации систем, собранных на AXI шинах. Что в комплекте, как использовать, как симулировать в Vivado и вне, и как тестировать AXI Slave с помощью AXI Master VIP.


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Прокачиваем скрипты симуляции HDL с помощью Python и PyTest

Posted on 17 Jan 2021 in Automation • Tagged with python • 11 min read

Концепт запуска HDL тестов через Pytest


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