Constant Reference in SystemVerilog: Is It Really Constant?

Posted on 14 Jan 2024 in Verification • Tagged with systemverilog • 4 min read

Usually, a programmer uses const ref for a method argument when they want to show an intention to have read-only variable that isn't a copy of an original one. And this works as a hint perfectly, but what 'constant' guarantees can the simulator actually provide? So, I've started digging...


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